Section and stack alignment

[swinchen]

Hi all,

I was wondering if anyone could point me to the documents that discuss stack and section alignment?

I have been looking through the linker script for the STM32F4xx series and notices that several output sections are 16-byte aligned (e.g. startup : ALIGN(16) SUBALIGN(16)) while others are 4-byte aligned (e.g. constructors : ALIGN(4) SUBALIGN(4)). The only reference I can find to section alignment is in the "ELF For Arm Architecture" (ARM IHI 0044E) and it states:

4.3.5 Section Alignment
There is no minimum alignment required for a section. However, sections containing thumb code must be at least
16-bit aligned and sections containing ARM code must be at least 32-bit aligned.
Platform standards may set a limit on the maximum alignment that they can guarantee (normally the page size).

So why the 16 byte (quad-word) alignment on certain sections? Why are the sections in .data and .bss 4-byte (word) aligned?


Finally can someone explain this:

5.2.1.2 Stack constraints at a public interface
The stack must also conform to the following constraint at a public interface:
SP mod 8 = 0. The stack must be double-word aligned.

What exactly is a "public interface" in this context? I have only heard that term in reference to object-oriented programming. Is this why the main_stack_base and main_thread_stack_base are 8-byte aligned?

I am just curious... I really am trying to get comfortable with the internals.

Thanks!
Sam

[Giovanni]

Hi,

You should get the EABI document from the ARM web site.

In brief, stacks can be aligned to 4 or 8 bytes at public interfaces (functions entry points) but 8 bytes is recommended by EABI.
RAM data can be aligned to 4 bytes boundary.

Anything in FLASH should be aligned to a FLASH page boundary, failing to do so can affects timings even for very small code changes, imagine critical loops sliding in and out a page boundary. Crossing a boundary usually takes wait states.

Giovanni

[swinchen]

Hmmm, I am having a hard time find the EABI document. I have found the "Base Standard ABI" and "Base Platform ABI" and the "Procedure Call Standard for the Arm Architecture" I can't seem to find anything that talks about alignment sections in RAM other than the quote I posted in my first post. I will have to read through these more carefully. If you have a link to the EABI document that would be greatly appreciated.


Are these http://i.imgur.com/2I3Ts9C.png the page boundaries? I have been through the datasheet for the device and the reference manual and can not find any reference to the page boundaries or wait states associated with them. I also noticed that FLASH is broken into larger regions as shown here:http://i.imgur.com/eQbCH3q.png. Given this information I can not see why the output section (and input sections) are forced to 16 byte alignment.


Thanks for the response!
Sam

[Giovanni]

The document is the one you mentioned, I got confused by the equivalent document for PPC.

About the flash, it can also be mentioned as size of the data bus on the flash, for example on the STM32F3:

Memory organization:
– Main memory block:
32 Kbits × 64 bits
– Information block:
1280 × 64 bits

Those 64bits are the the memory size that can be read with a single operation, reading across those pages add latency. See the flash section on the RM of your device.

Giovanni