Where did the BRR go?

[rew]

I have an application where in an interrupt I need to set and reset GPIOs quickly. When I want to reset bits, I used the BRR (Bit Reset Register).

For example:

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GPIOF->BRR = 1;

Now I've upgraded Chibios and this code no longer compiles. The compiler suggests a different register in the GPIO struct, and searching for that I found the GPIO_TypeDef struct which included that register as well as the BRR on my processor (STM32F030C8T6).

Turns out that:

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#define mGPIOF ((GPIO_TypeDef *)GPIOF)
   mGPIOF->BRR = 1;

Does work.

Why was "normal" access to GPIOF->BRR removed?????

[Giovanni]

Hi,

The PAL driver uses a different GPIO structure, you need to use the new one. Note that if you use the PAL port/pad functions then you are manipulating the BRR registers with no extra code, it is all inlined, there is no really need to manipulate the register directly.

Giovanni

[rew]

OK. So in advance, I've prepared the 32-bit word that sets and clears the right bits of that GPIO port when written to the BSRR (A total of precisely 8 bits need to be set and/or reset, the other 8 need to be left alone). Which function helps me do that?

In the documentation I find:

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#define palSetPort   (port,bits )   palWritePort(port, palReadLatch(port) | (bits))

I would say that this will never be able to be merged with a following ClearPort as the "volatile" on the ODR register declaration now requires at least a clock between the the set and clr operations.

[Giovanni]

You are right, set and clear at same time is not part of the API.

giovanni