Wrong checks on STM32_SDMMC_MAXCLK for H7 type1 lld
Posted: Sun Jan 15, 2023 4:10 pm
STM32_SDMMC_MAXCLK is not set in hal_lld_type1.h or hal_lld_type2.h and so defaults to 50Mhz which is way too low.
I suspect the values defined in hal_lld_type3.h are applicable to type1 and type2 as well
I suspect the values defined in hal_lld_type3.h are applicable to type1 and type2 as well