At the end of the last DMA transfer (number of transfers configured in the DMA controller’s
DMA_SxNTR register):
• No new DMA request is issued to the DMA controller if the DDS bit is cleared to 0 in the
ADC_CR2 register (this avoids generating an overrun error). However the DMA bit is
not cleared by hardware. It must be written to 0, then to 1 to start a new transfer.
• Requests can continue to be generated if the DDS bit is set to 1. This allows
configuring the DMA in double-buffer circular mode.
I think this bit should be set only if (grpp->circular).
Please see patch.
This does not solve issue in my case, but it definitely reduce ADC_SR_OVR irqs count. And may be this will allow to remove additional dmaStreamGetTransactionSize() check from ADC irq handler:
Code: Select all
/* Note, an overflow may occur after the conversion ended before the driver
is able to stop the ADC, this is why the DMA channel is checked too.*/
if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
/* ADC overflow condition, this could happen only if the DMA is unable
to read data fast enough.*/
if (ADCD1.grpp != NULL)
_adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
}I also have two more patches for ADC/DMA. One enabling DMA's FIFO for ADC channel and other enabling DMA's FIFO error IRQ.
But I still did not fix initial issue and don't want to waste your time reviewing something that possibly makes no scene.
