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ADCv4 incorrect ADC clock frequency
Posted: Wed Jul 16, 2025 6:34 pm
by jschall
- ChibiOS version or subversion revision number.master, a695d293
- Compiler.arm-none-eabi-gcc (GNU Arm Embedded Toolchain 10-2020-q4-major) 10.2.1 20201103 (release)
- Platform and board.STM32H753 REV V
- Nature of the problem.STM32_ADC12_CLOCK which was computed as 3.125 MHz. Measured ADC conversion time at max SMPR (should be 810.5 ADC clock cycles) by triggering ADC12 and TIM4 using TIM3 and then reading TIM4->CNT in the interrupt. The resulting latency was MUCH lower than could be achieved by an ADC running at 3.125 MHz. Back-computing the frequency based on the interrupt latency, the MINIMUM possible ADC frequency came out as ~14 MHz.
I am still trying to understand this. These are the numbers from my setup:
Code: Select all
STM32_PLLCLKIN = 25000000
STM32_PLL1_DIVM_VALUE = 25
STM32_PLL1_REF_CK = (STM32_PLLCLKIN / STM32_PLL1_DIVM_VALUE)
STM32_PLL1_DIVN_VALUE = 400
STM32_PLL1_VCO_CK = (STM32_PLL1_REF_CK * STM32_PLL1_DIVN_VALUE)
STM32_PLL1_DIVP_VALUE = 2
STM32_PLL1_P_CK = (STM32_PLL1_VCO_CK / STM32_PLL1_DIVP_VALUE)
STM32_SYS_CK = STM32_PLL1_P_CK
STM32_SYS_D1CPRE_CK = (STM32_SYS_CK / 1)
STM32_HCLK = (STM32_SYS_D1CPRE_CK / 4)
STM32_ADC_SCLK = (STM32_HCLK / 2)
STM32_ADC12_CLOCK = (STM32_ADC_SCLK / 4 / 2)
I have determined from a thorough reading of the reference manual that, at the very least, STM32_ADC_SCLK should be (STM32_SYS_CK / 2) instead of (STM32_HCLK / 2)
- Failure mode.BOOST bits are set incorrectly at the very least.
Re: ADCv4 incorrect ADC clock frequency
Posted: Wed Jul 16, 2025 6:39 pm
by Giovanni
Hi,
Please post your mcuconf.h.
Giovanni
Re: ADCv4 incorrect ADC clock frequency
Posted: Wed Jul 16, 2025 8:12 pm
by jschall
Code: Select all
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
this header is modelled on the one for the Nucleo-144 H743 board from ChibiOS
*/
#pragma once
#include <adc.h>
#define STM32H7xx_MCUCONF
#define STM32H743_MCUCONF
#define STM32H753_MCUCONF
#define STM32_HSECLK 25000000U
#define STM32_LSECLK 32768U
#define STM32_LSEDRV (3U << 3U)
/*
* General settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_SYS_CK_ENFORCED_VALUE STM32_HSECLK
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#define STM32_NOCACHE_SRAM3 TRUE
/*
* PWR system settings.
* Reading STM32 Reference Manual is required.
* Register constants are taken from the ST header.
*/
#define STM32_VOS STM32_VOS_SCALE1
#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
#define STM32_PWR_CR2 (PWR_CR2_BREN)
#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)
#define STM32_PWR_CPUCR 0
/*
* Clock tree static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_HSI_ENABLED FALSE
#define STM32_LSI_ENABLED FALSE
#define STM32_CSI_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_HSIDIV STM32_HSIDIV_DIV1
/*
* PLLs static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_PLLSRC STM32_PLLSRC_HSE_CK
#define STM32_PLLCFGR_MASK ~0
/*
setup PLLs based on HSE clock
*/
#if STM32_HSECLK == 8000000U
// this gives 400MHz system clock
#define STM32_PLL1_DIVM_VALUE 1
#define STM32_PLL2_DIVM_VALUE 1
#define STM32_PLL3_DIVM_VALUE 2
#elif STM32_HSECLK == 16000000U
// this gives 400MHz system clock
#define STM32_PLL1_DIVM_VALUE 2
#define STM32_PLL2_DIVM_VALUE 2
#define STM32_PLL3_DIVM_VALUE 4
#elif STM32_HSECLK == 24000000U
// this gives 400MHz system clock
#define STM32_PLL1_DIVM_VALUE 3
#define STM32_PLL2_DIVM_VALUE 3
#define STM32_PLL3_DIVM_VALUE 6
#elif STM32_HSECLK == 25000000U
#define STM32_PLL1_DIVM_VALUE 25
#define STM32_PLL2_DIVM_VALUE 25
#define STM32_PLL3_DIVM_VALUE 25
#else
#error "Unsupported HSE clock"
#endif
#if (STM32_HSECLK == 8000000U) || (STM32_HSECLK == 16000000U) || (STM32_HSECLK == 24000000U)
// common clock tree for multiples of 8MHz crystals
// clock in 8mhz
#define STM32_PLL1_DIVN_VALUE 100
#define STM32_PLL1_DIVP_VALUE 2
#define STM32_PLL1_DIVQ_VALUE 8
#define STM32_PLL1_DIVR_VALUE 2
#define STM32_PLL2_DIVN_VALUE 25
#define STM32_PLL2_DIVP_VALUE 2
#define STM32_PLL2_DIVQ_VALUE 2
#define STM32_PLL2_DIVR_VALUE 2
#define STM32_PLL3_DIVN_VALUE 72
#define STM32_PLL3_DIVP_VALUE 3
#define STM32_PLL3_DIVQ_VALUE 6
#define STM32_PLL3_DIVR_VALUE 9
#elif STM32_HSECLK == 25000000U
#define STM32_PLL1_DIVN_VALUE 400
#define STM32_PLL1_DIVP_VALUE 2
#define STM32_PLL1_DIVQ_VALUE 4
#define STM32_PLL1_DIVR_VALUE 2
#define STM32_PLL2_DIVN_VALUE 200
#define STM32_PLL2_DIVP_VALUE 2
#define STM32_PLL2_DIVQ_VALUE 2
#define STM32_PLL2_DIVR_VALUE 2
#define STM32_PLL3_DIVN_VALUE 192
#define STM32_PLL3_DIVP_VALUE 2
#define STM32_PLL3_DIVQ_VALUE 4
#define STM32_PLL3_DIVR_VALUE 6
#endif // 8MHz clock multiples
#define STM32_PLL1_ENABLED TRUE
#define STM32_PLL1_P_ENABLED TRUE
#define STM32_PLL1_Q_ENABLED TRUE
#define STM32_PLL1_R_ENABLED TRUE
#define STM32_PLL1_FRACN_VALUE 0
#define STM32_PLL2_ENABLED TRUE
#define STM32_PLL2_P_ENABLED TRUE
#define STM32_PLL2_Q_ENABLED TRUE
#define STM32_PLL2_R_ENABLED TRUE
#define STM32_PLL2_FRACN_VALUE 0
#define STM32_PLL3_ENABLED TRUE
#define STM32_PLL3_P_ENABLED TRUE
#define STM32_PLL3_Q_ENABLED TRUE
#define STM32_PLL3_R_ENABLED TRUE
#define STM32_PLL3_FRACN_VALUE 0
/*
* Core clocks dynamic settings (can be changed at runtime).
* Reading STM32 Reference Manual is required.
*/
#define STM32_SW STM32_SW_PLL1_P_CK
#define STM32_RTCSEL STM32_RTCSEL_NOCLK
#define STM32_D1CPRE STM32_D1CPRE_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV4
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV1
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV1
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV1
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV1
/*
* Peripherals clocks static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_MCO1SEL STM32_MCO1SEL_HSE_CK
#define STM32_MCO1PRE_VALUE 4
#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
#define STM32_MCO2PRE_VALUE 4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_HRTIMSEL 0
#define STM32_STOPKERWUCK 0
#define STM32_STOPWUCK 0
#define STM32_RTCPRE_VALUE 8
#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
#define STM32_QSPISEL STM32_QSPISEL_HCLK
#define STM32_FMCSEL STM32_QSPISEL_HCLK
#define STM32_SWPSEL STM32_SWPSEL_PCLK1
#define STM32_FDCANSEL STM32_FDCANSEL_PLL1_Q_CK
#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK
#define STM32_SPI45SEL STM32_SPI45SEL_PLL2_Q_CK
#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK
#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK
#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_DISABLE
#define STM32_USBSEL STM32_USBSEL_PLL3_Q_CK
#define STM32_I2C123SEL STM32_I2C123SEL_PLL3_R_CK
#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK
#define STM32_USART16SEL STM32_USART16SEL_PCLK2
#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1
#define STM32_SPI6SEL STM32_SPI6SEL_PLL2_Q_CK
#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK
#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK
#define STM32_ADCSEL STM32_ADCSEL_PLL3_R_CK
#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4
#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_ADC_DUAL_MODE TRUE
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC12 FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_SAMPLES_SIZE 32
#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_PWM_USE_TIM1 TRUE
#define STM32_GPT_USE_TIM3 TRUE
#define STM32_GPT_USE_TIM4 TRUE
#define STM32_SDC_USE_SDMMC1 TRUE
#define STM32_SPI_USE_SPI1 TRUE
#define STM32_SPI_USE_SPI5 TRUE
#define STM32_UART_USE_USART3 TRUE
#define STM32_USB_USE_OTG1 TRUE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
#define HAL_USE_GPT TRUE
#define STM32_DMA_REQUIRED
Oh, also, I'd like to clarify the ChibiOS version:
I'm using an older version of ChibiOS, but I've pulled in hal_adc_lld from master. It is possible that master does not have this issue, but as far as I can tell from the reference manual, using HCLK in the computation of ADC clock is wrong.
Re: ADCv4 incorrect ADC clock frequency
Posted: Thu Jul 17, 2025 9:03 am
by Giovanni
Hi,
Your ADC clock source (STM32_ADCSEL) is set to STM32_ADCSEL_PLL3_R_CK, is it meant to be that way?
Giovanni
Re: ADCv4 incorrect ADC clock frequency
Posted: Tue Aug 26, 2025 9:18 am
by Giovanni
Any news?
Giovanni
Re: ADCv4 incorrect ADC clock frequency
Posted: Sun Dec 28, 2025 9:48 am
by Giovanni
Closing, I recommend trying more recent code.
You may try (un)defining STM32_ENFORCE_H7_REV_XY, it should force a different clock calculation and fix boost.
Giovanni