ChibiOS Free Embedded RTOS

i may add my 5cent for FDCANv2 on STM32H7A3 …


⋅ it actually supports more interrupts then RX-FIFO-FULL when receiving frames: there is RX-FIFO-WATERMARK and RX-FIFO-NEWMESSAGE (see RM0455, 2457/2966, FDCAN_IE bit 0, 1, 4 and 5). the testhal CAN code works properly, as it generates a lot ...

i am using Fedora 40, which comes with
$ grep --version
grep (GNU grep) 3.11
Copyright (C) 2023 Free Software Foundation, Inc.
License GPLv3+&#58; GNU GPL version 3 or later <https&#58;//gnu&#46;org/licenses/gpl&#46;html>&#46;
This is free software&#58; you are free to change and ...

it seems, DAC2 is missing for / does not compile on STM32H7A3 / STM32H7B3 / STM32H7B0, so far. those H7 variations contain DAC1, which has 2 channels, as well as DAC2, which has only one channel.

to compile, when having #define STM32_DAC_USE_DAC2_CH1 TRUE in mcuconf.h, the following patch is ...

just a minor cosmetic thing:
make&#91;1&#93;&#58; Entering directory 'src'
egrep&#58; warning&#58; egrep is obsolescent; using grep -E
grep&#58; warning&#58; stray \ before #
egrep&#58; warning&#58; egrep is obsolescent; using grep -E
grep&#58; warning&#58; stray \ before #
egrep&#58; warning&#58 ...

as of my knowledge, the 4k backup sram requires
* PWR->CR1 |= PWR_CR1_DBP_Msk; # disable backup protection
* PWR->CR2 |= PWR_CR2_BREN_Msk; # backup regulator enable
* while &#40;!&#40;PWR->CR2 & PWR_CR2_BRRDY_Msk&#41;&#41;; # backup regulator ready

* i think the values stored in backup sram will ...

this may be related to viewtopic.php?f=35&t=6352

hi,

in os/hal/ports/STM32/STM32H7xx/platform.mk , as well as os/hal/ports/STM32/STM32H7xx/platform_type2.mk , there is RTCv2 selected. the STM32H7A3 , STM32H7B3 and STM32H7B0 (Q and no-Q variants) have something, that is much more similar to RTCv3 , it seems.

should those variations of the STM32H7 ...

for the STM32H7A3, the maximum is 280Mhz in VOS0.

i also can't make out these constrains from os/hal/ports/STM32/LLD/SDMMCv2/hal_sdc_lld.h
#if STM32_HAS_SDMMC1 && (STM32_SDMMC1CLK * 10 > STM32_HCLK * 7)
#error "STM32_SDMMC1CLK must not exceed STM32_HCLK * 0&#46;7"
#endif

#if STM32_HAS_SDMMC2 && (STM32_SDMMC2CLK * 10 > STM32_HCLK * 7)
#error ...

/3 did not work for me (did not come up, maybe an exception some place), but /5 did!
* 24 / 3 * 70 / 2 = 280 (assuming testOslib results are 100%)
* 24 / 15 * 175 / 1 = "impossible" 280 --> seems to work as expected, about 100% performance (testOslib)
* 24 / 3 * 70 / 3 = "impossible" 187 --> did not ...