Search found 37 matches
- Mon Feb 09, 2026 8:32 am
- Forum: STM32 Support
- Topic: STM32H7 Silicon errata for SPI peripheral
- Replies: 6
- Views: 3492
Re: STM32H7 Silicon errata for SPI peripheral
If I had to guess, that means the bug isn't exactly "simplex TX followed by DMA RX" but is actually something like "any operation without RX MINC set, followed by an operation with RX MINC set"
- Mon Feb 09, 2026 8:26 am
- Forum: STM32 Support
- Topic: STM32H7 Silicon errata for SPI peripheral
- Replies: 6
- Views: 3492
Re: STM32H7 Silicon errata for SPI peripheral
The unmodified SPI MMC driver runs in to this on H7. Here's the github issue where I debugged it and followed it back to the errata sheet: https://github.com/rusefi/rusefi/issues ... -785337711
- Wed Feb 04, 2026 9:28 am
- Forum: STM32 Support
- Topic: STM32H7 Silicon errata for SPI peripheral
- Replies: 6
- Views: 3492
Re: STM32H7 Silicon errata for SPI peripheral
We do it there before a send as well, but I'm pretty sure it's only required before receive or exchange (and should get moved to the spi lld).
- Fri Jan 23, 2026 7:18 am
- Forum: Bug Reports
- Topic: Another stm32h7 dual mode ADC bug
- Replies: 3
- Views: 3574
Another stm32h7 dual mode ADC bug
In os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c, if you have dual mode ADC1/2 enabled, and also ADC3 enabled, the code starting on line 807 (adcp->adcm->CFGR2 = grpp->cfgr2; etc) stomps over the master ADC configuration set in lines 765-780. It's missing an else case there and just runs ...
- Wed Jan 22, 2025 8:38 am
- Forum: Bug Reports
- Topic: Thread stack alignment assertion
- Replies: 2
- Views: 20878
Re: Thread stack alignment assertion
Works for me now, thanks!
- Wed Jan 22, 2025 1:32 am
- Forum: Bug Reports
- Topic: Thread stack alignment assertion
- Replies: 2
- Views: 20878
Thread stack alignment assertion
Hi, I'm running off of pretty close to master on GitHub, and I'm hitting this assertion: m (I'm not doing anything unusual, it's a normal statically allocated thread I'm trying to start). STM32F0, so armv6m.
stktop gets aligned on PORT_NATURAL_ALIGN (4), but then we check that it's aligned to PORT ...
stktop gets aligned on PORT_NATURAL_ALIGN (4), but then we check that it's aligned to PORT ...
- Fri Dec 20, 2024 9:04 am
- Forum: Bug Reports
- Topic: Build failure if CH_CFG_USE_REGISTRY is false
- Replies: 2
- Views: 19769
Re: Build failure if CH_CFG_USE_REGISTRY is false
And another one: If you define CH_CFG_USE_REGISTRY but not CH_DBG_ENABLE_STACK_CHECK, then chRegFindThreadByWorkingArea is a missing symbol.
- Fri Dec 20, 2024 9:01 am
- Forum: Bug Reports
- Topic: Build failure if CH_CFG_USE_REGISTRY is false
- Replies: 2
- Views: 19769
Build failure if CH_CFG_USE_REGISTRY is false
Latest ChibiOS from GitHub doesn't build if CH_CFG_USE_REGISTRY is false. See near the end of chthreads.c function chThdObjectInit, there's a line that says
(void)name;
But there's no longer a parameter called name!
(void)name;
But there's no longer a parameter called name!
- Sun Oct 20, 2024 11:51 pm
- Forum: Bug Reports
- Topic: USB CDC ACM and 64 bytes transaction
- Replies: 23
- Views: 53387
Re: USB CDC ACM and 64 bytes transaction
Does this reproduce on an STM32H7? It uses a different USB IP and driver.
- Sat Sep 17, 2022 9:25 pm
- Forum: Bug Reports
- Topic: Errata STM32: RTC calendar registers are not locked properly
- Replies: 9
- Views: 10689
Re: Errata STM32: RTC calendar registers are not locked properly
That does look better. I think the exact bug before was that if you managed to exactly catch a subsecond rollover (ie, oldssr != ssr on the first iteration), then you had to wait a full second for it to "come back around".
Is it guaranteed that we need a loop, instead of the if originally proposed ...
Is it guaranteed that we need a loop, instead of the if originally proposed ...