Rework Makefile to be makefile name independent

[jafrey]

In working with the Simulink project I've run into troubles with the Makefile. It automatically generates a make file based on the project. For example chibiOS_test.mk. And then it is called with make -f chibiOS_test.mk.

However in the 'rules.mk' file it references Makefile and I get an error "No rule to make target Makefile".

I can't seem to find a way to dereference the called Makefile using make macros, is it possible to do this?

[Giovanni]

I think it is not possible, why don't just call the file Makefile?

Giovanni

[TexZK]

Why don't you create a dummy Makefile which simply includes your own? And, if I recall correctly, there's also a target hook you might exploit.

[jafrey]

Why don't you create a dummy Makefile which simply includes your own? And, if I recall correctly, there's also a target hook you might exploit.

This is what I ended up doing. Simulink is also looking for a success string in the build log file. So I made a new custom target that depends on all and then had it echo back a success.

Code: Select all

include chibiOS_Config_Model.mk

simulink: all
   ### Created and Compiled chibiOS_Config_Model

Then I made a custom make command (the default one it generates isn't very good) that calls

Code: Select all

make -j 8 simulink

Works like a charm. I can go straight from simulink -> STM32F4Discovery board now with no errors.

[jafrey]

What does the recursive call here:

Code: Select all

$(ACOBJS) : $(OBJDIR)/%.o : %.c Makefile

do? I've dug through the make manual and can't seem to find a rule that matches that.

[Giovanni]

Good question

I don't remember the details.

[efuentes]

I think it means that any changes to %.c or the Makefile will cause the source file to be recompiled.